Programmable device arrays are basic building blocks for configurable logic circuits used in computer systems. Examples of programmable device arrays include Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Arrays (CPLA), etc.
Current FPGAs use either Static Random Access Memory (SRAM) cells or antifuses to program the logic cells and crossbar switches (i.e., a matrix switch connecting multiple inputs to multiple outputs). Antifuse based FPGAs are one-time programmable only, and hence they have limited use. SRAM-based FPGAs also suffer from a couple of known problems. For example, the logic cells typically have high leakage power. Also, though SRAM uses bi-stable latching circuitry to store each bit, it is still a volatile type of memory in the sense that data is eventually lost if the memory device is not externally powered. Therefore, the entire SRAM needs to be reloaded with configuration data whenever the FPGA is powered on. This necessitates an external non-volatile storage (e.g., Flash storage), and dedicated Input/Outputs (I/Os) for configuration, and leads to relatively long programming time on startup. An additional disadvantage is that there may be security issues associated with storing configuration data in off-die memory arrays, requiring additional complex encryption schemes.
Non-volatile types of RAMs have characteristics that are favorable for embedding in high-speed high-density logic circuitry. Spin Transfer Torque Random Access Memory (STTRAM) is a type of non-volatile RAMs that is typically used for more conventional memory circuits, such as, cache, secondary storage etc. Current high-speed high-density logic circuits like FPGAs/CPLAs typically do not employ STTRAM or other STT-based elements. Some researchers have proposed to hybridize conventional Complementary Metal Oxide Semiconductor (CMOS)-based FPGA design with STTRAM to implement a CMOS-STTRAM non-volatile FPGA configuration. See, for example, the article entitled, “Hybrid CMOS-STTRAM Non-Volatile FPGA: Design Challenges and Optimization Approaches,” by Paul et al., pp. 589-592, 2008 IEEE/ACM International Conference on Computer-Aided Design. However, there is room to bring STTRAM closer to logic level and embedding non-volatile memory bits in reconfigurable logic to be used in high-volume computer architectures and interfaces. The present disclosure addresses the shortcomings of the currently available solutions by proposing devices using STT-based elements and associated manufacturing process thereof.